SMI Implements Centipede’s Massively Parallel Test for MEMS


San Jose, Calif. (May 15, 2013) – Silicon Microstructures, Inc.  (SMI) a leader in MEMS Pressure Sensors, announces test-in-tray for parallel testing of MEMS based pressure sensors in volume production. SMI has put test-in-tray processing into production for automated handling and testing. Pressure, temperature and calibration tests are performed on an array of devices held in the tray. The automated test-in-tray handler, supplied by Centipede Systems, provides rapid thermal conditioning over any computer controlled profile between -55⁰C. and +150⁰C. Independently controlled pressure ports allow dynamic leak testing over the full range of temperatures and pressures for effective screening of latent defects.

“Calibration and testing of MEMS pressure sensors over a full combination of pressures and temperatures allows us to provide sensors with better accuracy and reliability to our customers,” states Mr. Rainer Cholewa, President and CEO of SMI.  “I am delighted with the inherent efficiency of test-in-tray processing so that we can supply high performance MEMS pressure sensors to our customers cost-effectively.”

“The test-in-tray format greatly simplifies handling and thermal management of MEMS devices under test,” says Dr. Tom Di Stefano, President of Centipede Systems. “A full tray of devices is indexed into the test position, where a mini-chamber encloses the tray of devices in a thermally controlled environment.  The temperature and pressure stimuli are computer controlled to test and calibrate the parts rapidly through any combination of test conditions.” Di Stefano adds, “The test-in-tray format allows unlimited parallelism for added productivity in the future.”

Accurate testing of pressure sensors is complicated by thermally induced interactions and leaks. Testing a tray of devices in a mini-chamber facilitates the testing process. “Testing in a tray format has increased throughput many times over,” claims Mr. Holger Doering, COO at SMI.  “Only the mini-chamber must be heated and cooled during the test, greatly speeding up the process of thermal testing. Also, since thermal, electrical and pressure connections are faster and more reliable when done in the tray format, the process is more easily automated.”

Di Stefano claims “SMI is a leader in adopting test-in-tray for MEMS device testing, and I am pleased with the cooperation between our companies in introducing test-in-tray methods into production.” He further asserts, “the test-in-tray paradigm offers a solution to the parallelism bottleneck and provides a standard handling format for automation of the semiconductor entire back end process.”

About SMI:

SMI offers high performance MEMS based pressure sensors to a range of industries, based on application-specific ICs, sensors, complete Microsystems, and advanced packaging.  For more information, visit

About Centipede Systems, Inc.
Centipede Systems is a leader in massive parallel testing. The company supplies tray handling equipment and fixtures including FlexFrame™ tray carriers, socket cartridges, thermal management systems and test mini-chambers. Centipede is headquartered in San Jose, CA.

Raul Figueroa
Director of Global Marketing
+1 408.473.9797

Centipede Systems, Inc.
Dr. Thomas Di Stefano, President
+1 408.321.8201

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2011 SEMI Award for North America Given to Thomas DiStefano, John W. Smith, Jr. and Michael Warner for Chip Scale Packaging Technology

HALF MOON BAY, Calif. – January 11, 2011 – SEMI today named Thomas DiStefano, John W. Smith, Jr. and Michael Warner as recipients of the SEMI Award for North America for contributions to the development and commercialization of Micro Ball Grid Array (μBGAÒ ) technology.  This advancement led to many forms of semiconductor chip scale packaging that enabled cost effective miniaturization. It has had a significant impact on the proliferation of products with smaller form factors, such as handheld phones, recorders, games and other electronics that have since become common. The SEMI Award for North America is the association’s highest honor for technical contribution to the semiconductor industry.  The industry awards will be presented during a banquet at the 2011 SEMI Industry Strategy Symposium (ISS) in Half Moon Bay, California this evening.


<b>Recipients John Smith, Tom Di Stefano, and Mike Warner<b>

Recipients John Smith, Tom Di Stefano, and Mike Warner


“Our industry honors Tom DiStefano, John Smith and Michael Warner for their combined efforts to commercialize Micro Ball Grid Array technology while at Tessera Technologies,” said Stanley T. Myers, president and CEO of SEMI. “This critical packaging technology was an important development in the proliferation of smaller personal electronic devices that have spurred the market for semiconductor devices.”


Bill Bottoms presenting award to Tom Di Stefano

Bill Bottoms presenting award to Tom Di Stefano


Dr. DiStefano was the founding president of Tessera Technologies and a co-founder of ChipScale Review. DiStefano helped to build Tessera into a world leader in miniaturized packaging. Royalties from U.S. Patents coauthored by DiStefano produced well above $1Billion revenue for Tessera. John W. Smith, Jr. joined Tessera in 1992 as its CEO where he served until his retirement in 2000. Michael Warner, a Tessera Fellow, joined the company in 1994 as the corporate officer responsible for developing products employing µBGA solutions for government, medical and commercial applications.

“The introduction of chip scale packaging enabled a decrease in package size and an increase in package frequency while reducing the total power required,” said Bill Bottoms, chairman of the SEMI Award Advisory Committee.  “This innovation is now the packaging solution of choice for most memory devices and a significant number of logic devices.  It was initially adapted to meet performance requirements and the high-volume commercialization led to its widespread adaption as a lower-cost packaging alternative.”

The SEMI Award was established in 1979 to recognize outstanding technical achievement and meritorious contribution in the areas of Semiconductor Materials, Wafer Fabrication, Assembly and Packaging, Process Control, Test and Inspection, Robotics and Automation, Quality Enhancement, and Process Integration.

The award is the highest honor conferred by SEMI. It is open to individuals or teams from industry or academia whose specific accomplishments have broad commercial impact and widespread technical significance for the entire semiconductor industry.  Nominations are accepted from individuals of North American-based member companies of SEMI. Past award recipients include Walter Benzing and Mike McNealy, Ken Levy, Jean Hoerni, Dan Maydan, Robert Akins and Igor Khandros, among others.

About SEMI

SEMI is the global industry association serving the manufacturing supply chains for the microelectronic, display and photovoltaic industries. SEMI member companies are the engine of the future, enabling smarter, faster and more economical products that improve our lives. Since 1970, SEMI has been committed to helping members grow more profitably, create new markets and meet common industry challenges. SEMI maintains offices in Austin, Beijing, Bengaluru, Berlin, Brussels, Grenoble, Hsinchu, Moscow, San Jose, Seoul, Shanghai, Singapore, Tokyo, and Washington, D.C. For more information, visit

Association Contact

Deborah Geiger/SEMI
Tel: 1.408.943.7988

Wanted: A backend transport standard for burn-in and test

Previously Published June 2009

Leaders in the semiconductor industry have learned well the lessons of the learning curve that underlies Moore’s Law, as they assiduously seek ways to accelerate their own learning curves. Fundamentally, the business is simple: Gain a few percentage points in the slope of your learning curve and you win.

The converse is also true. At some level we all understand this, but few execute as well as Intel, a clear leader in semiconductor manufacturing. Backend packaging and test could pick up a few pointers from their wafer fab experience. In the past several years, Intel has moved its front-end fabs to full lights-out automation to accelerate their learning curve. The benefits go well beyond scrimping on the cost of labor. As explained by Tom Franz, VP/GM of fab/sort at Intel, the focus is on tool and process learning instead of moving WIP around the line1.

Over a two-year period, Intel improved cycle time by 50 percent, according to Franz. Over the same period, Intel improved tool utilization by 10-30 percent.

To control CAPEX, standardization of tools is essential in allowing tool reuse. We learn from this fab experience that full automation enables rapid learning and propels the industry forward.

A key enabler2 for lights-out automation in the fab is a single wafer front-opening unified pod (FOUP), a standardized pod. Wafers are transported through the fab in the FOUP, controlled by a logistics system that keeps WIP efficiently in front of tools.

The single-wafer FOUP does not tie-up WIP sitting in a stack of wafers. Importantly, equipment suppliers can build efficient tools to one standard wafer interface, avoiding the cost, logistics problems and delays entailed in a plethora of custom fixtures and protocols.

So, what about backend packaging and test, which consumes an increasing share of the cost of IC manufacturing?

Some inefficiency is due to a proliferation of probers, sockets, fixtures, handlers, protocols and the handling of piece parts. However, it is not that engineering has stood still in this arena.

Efforts are made to rationalize processes and standards. A move toward wafer-level processing promises to simplify packaging. Parallel testing of chips, both memory and logic, has improved efficiency and throughput. Clearly, however, more remains to be done.

Borrowing a chapter from the fab, a standard for transport through backend burn-in and test sectors is the key to enabling full automation. A logical unit of transport is a tray with alignment features and standard sizes.

Standardized trays serve the same enabling function provided to the fab by the singlewafer FOUP. Equipment can then use standardized handing, well-suited to automation, doing away with custom fixturing and piece-part handling.

Furthermore, for lights-out automation, the transport must be run with virtually no maintenance and must eliminate jams, cleaning, jury-rigging and other diversions.

Test-in-Tray (TnT) can conceivably run from wafer dice through finishing, burn-in, test, trim and mark-and-pack. The process flow depends upon device type and application, but handling protocols can be standardized industry-wide.

Even burn-in, the much-reviled, no-value-added process, can be automated to test during burn-in to derive valuable test information and minimize time in a more intelligent process. Arrays of parts in trays can be moved in and out of burn-in pods automatically. Throughout this process flow there is no need for handling individual parts by humans or robots.

The adoption of TnT is moving forward inMEMS applications, where standards are needed for handling a widely diverse universe of device types.Astandard tray, shown above, holds 32 MEMS devices in a tray 100mm x 240mm. Trays are adapted for the automatic handling and alignment needed in test procedures at temperatures from -65oC to +180oC.

Trays are also adaptable to device types from MEMS sensors to CSPs, BGAs and flip chips, all within the same handling standards. Access to the contact array as well as to cooling surfaces is accommodated by open top- and bottom trays. Inserts adapt the tray transport to the specific device type.

TnT offers the potential of enabling full lights-out automation of burn-in and test, greatly accelerating the learning curve. The backend can be closely integrated to provide fast information feedback for rapid learning. Lights-out production trumps the race to low-wage venues and greatly reduces waste in custom fixturing of incompatible tools. The competitive advantage of TnT is compelling.

1. Presented by Tom Franz, VLSI Research webcast, 7/25/
2. From Allen Ibara, CEO, Phiam Inc.

Attending Semicon?

The Test In Tray User Group is a highlight of the test solutions session at 10:30 on July 16 in North Hall.

Towards a More Efficient Test Paradigm

Previously Published April of 2009

There is a growing consensus that test and burnin (TBI) requires a new approach. SEMI’s CAST consortium is just the latest attempt to bring focus to an aspect of this looming problem.

TBI consumes an increasing portion of the manufacturing cost of semiconductor devices. The problem continues to worsen as test time grows with increasing device complexity.

And “no value-added” burn-in refuses to go away, as high-margin products push technology to limits that require screening for latent defects. Conversely, devices that do not need burn-in are typically low-value commodities.

The response of the test community has been to move toward more parallel testing and intelligent burn-in schemes—improvements all within a standard, time-proven backend paradigm.

Parallel testing of DRAMs has been extended to full 300mm wafer test. Parallelism in test of logic is moving from 8-up toward 16-up testing. And test during burn-in (TDBI) extracts more value from necessary burn-in of high-complexity parts.While these improvements help, more is needed in the way of test efficiency.

The way forward appears to involve more parallelism and standardized automation. Automatic handling of large arrays of parts is a logical approach to facilitate the cost reduction of parallel testing and burn-in.

Strip testing or Test-in-Tray (TnT) permit automated handling of large arrays in a standard format.

Pioneered a decade ago by Jack Kessler at Amkor, strip testing is still used in specialized cases where devices are fabricated in strip arrays.

TnT, a close cousin of strip test, is more broadly applicable across a large variety of package types from MEMS sensors to WLP and TSV devices.

As a platform for broad standardization, TnT promises to be a powerful facilitator for the massively parallel testing of large arrays of devices.

Surmounting a major obstacle to the adoption of strip test, TnT does not require a return from the test floor to package processing for the final steps of lead forming and singulation.

TnT users enjoy the same benefits promised by strip testing while potentially enabling adoption across major segments of the industry.

Parallel testing of large TnT arrays is independent of the method used for fabrication of the device. The size of the array is limited only by the number of test channels.

Similar to strip testing, TnT allows automatic handling of arrays throughout the testflow from burnin to final test. Because each part remains in its array position in bar-coded trays, tracking of individual devices is relatively simple throughout the process.

And automation uses simple, standard transports for jam-free operation, with manual intervention at a minimum.All contribute to a dramatically increased throughput for the test operation.

Charles Schleich, manufacturing director at Atmel, San Jose, claims that “strip test provides a three-fold increase in throughput for a given test cell.”

Schleich, an early advocate of TnT, first introduced the author to the advantages of testing devices in trays. The increased efficiences derive from the fast transport of large arrays through the test process.

The device remains in the array without the need for pick-and-place of devices at each step.As a practical matter, testing in strip format is accomplished first because certain classes of parts are packaged in strip format and the packaging paradigm can easily be extended to testing.

The key technology in any parallel test scheme is the contactor system, including the connector or probe, the alignment mechanism and the interconnections.

Reliable, low-maintenance contactors are needed for the large arrays of high-performance devices, many of which operate at high current levels.

Fine-pitch contactor spacing is an additional challenge in these dense arrays. And unlike test sockets where periodic cleaning and maintenance allow reliable contact, contactors in arrays of upwards of 50,000 terminals must provide reliable contact without onerous and costly maintenance.

Present-day contactors used for test sockets do not scale well to these extreme demands for reliability. It appears that TnT will drive a next leg upward in contactor technology needed for massively parallel testing.

The added demands of operation at high temperature and power for tray burn-in are particularly difficult with current contactors, mandating substantial advances in technology.

Thermal management becomes an issue for parallel testing of high performance processors and high power devices. Cooling a dense array of 100Wprocessors is a challenge—64 such devices dissipate 6.4 KWin a small area.

While thermal management is a challenge, it is not insurmountable considering the potential cost reduction involved. Standardization is an essential element needed for adoption and growth of the Test-in-Tray industry.

While TnT promises the benefits of strip testing, it allows the broad application and standardization across a broad spectrum of package types fromMEMS sensors to high-performance processors. Importantly, TnT breaks the test format free from the format used in package production.

For example, an array of 32 devices may be packaged in a strip format, but the test can be most efficiently performed in a tray of 128 devices tested in parallel. Conversely, small devices may be packaged in a tightly spaced array of 256 devices, while testing can be performed best on 32 devices in an array of fixed centers.

While quite adaptable, standards must be set for tray size, marking, features and materials. The tray format can be standardized to a common format, allowing the same automation, transport and data tracking to be used for a very broad range of device types.

The technological challenges we face in implementing TnT are known and not insurmountable, particularly with the tremendous cost savings of fully automated parallel test enabled by TnT.

Lights out!

Previously Published July 2009

Many anticipate that the next upturn in the semiconductor industry is around the corner. But when? And how? At some level we understand that each successive cycle entails new approaches and methods, winners and losers.

Winners develop new technologies during the slump and use them to get ahead (i.e., of competitors) in the next wave. The downturn presents a fresh opportunity to reflect on trends in the industry and perhaps perceive shifts in direction.

Let’s take a moment to peer a bit into the future and outline a few challenges it presents for microconnection technologies. In tuning our antennae to detect new currents in the ether, we sense the beginnings of a possible wave of change in manufacturing protocols.

It appears here and there as full automation so complete and well-integrated that processes seem to run themselves. That is to say, the factory can run with the lights turned out and without direct human intervention.

The concept of lights-out manufacturing is not new, but its time may have come. If so, what does it mean to us in the contactor, socket and probe industry?

Lights-out automation would have a significant impact on semiconductor electronics. It transcends differential labor rates and breaks the race to lower labor cost venues. Manufacturing can be done anywhere: close to development to accelerate learning; close to the market for fast response; or in IP friendly environments.

More importantly, it frees-up resources to focus on rapid learning. A steep learning curve is particularly important in semiconductor electronics, where a competitor who falls a few percentage points behind the curve may be out of manufacturing in a short period of time.

Take a lesson from Intel, a perennial manufacturing powerhouse that has increasingly moved toward lights-out automation in semiconductor production.

This approach allows people to concentrate on improving the tools and processes instead of moving WIP around the wafer fab1. Tools and equipment are standardized to allow reuse and rapid reconfiguration.

The automation and standardization, coupled with Intel’s copy-exactly strategy, preserves and accelerates learning. In essence, manufacturing is a learning machine that can be used as a formidable competitive weapon.

The simplest implementation of lights-out manufacturing is the replacement of a human arm with a robotic arm.

The simplest implementation of lights-out manufacturing is the replacement of a human arm with a robotic arm.


Lights-out manufacturing has been attempted before with limited results. Mea culpa, I spent the late 1980s at the IBM Manufacturing Research Center, dedicated to accelerating IBM’s learning curve. Lights-out manufacturing, as it was understood at the time, largely involved mechanization of manufacturing processes.

In a sense, the simplest implementation involves replacement of a human arm with a robotic arm. Research centers at that time explored advances in robotics and automation. The outcome of all these efforts was often inflexible mechanization rather than intelligent manufacturing.

Early attempts at lights-out automation fizzled because people in manufacturing tend to perform more than mindless mechanical movements. People in manufacturing are involved in a complex set of interactions involving observation, problem solving, judgment, rapid reconfiguration, and learning.

Without people on the factory floor, who will detect and eliminate snags and problems in manufacturing? Who will see that something “doesn’t look right”? That a misaligned loader is causing jams in product flow? Or that a dirty socket is causing retest?

To reap the benefits of lights-out manufacturing, the semiconductor industry needs more than mechanization. A standardized means of transport is central to automation,

As reviewed in a recent MicroConnections article, 2 Test-in-Tray can do for the backend what the single wafer FOUP did for the wafer fab. Beyond transport, standards for interfaces to equipment, such as the test cell, are needed.

Processes, measurements and tests must be extremely reliable, requiring virtually no maintenance. Everyone in the industry is impacted, including semiconductor manufacturers, fabless IC companies, MEMS suppliers and OEMs.

So, what does this have to do with connectors, sockets, and probes? Plenty! The semiconductor backend is a major market for micro-connectors of all kinds. The requirements are as demanding as the margins are attractive. Clearly, a paradigm shift toward lights-out automation in this sector is important to us.

To meet the challenge, significant innovations are needed to overcome impediments to maintenance- free automation.


Intel is the leader in standardized processing in the semiconductor industry (Intel photo)


For example, sockets and wafer probes are notoriously temperamental, requiring attention, alignment and cleaning. Retest of poorly contacted parts makes a mess of product flow.

Fixturing is expensive and often incompatible across handlers and testers. Burn-in sockets and ovens are not easily compatible with full automation.

Connectors and sockets are often custom designs that are expensive, long-lead items. These challenges are an opportunity for the test, socket and connector industry to provide enabling solutions toward burn-in and test environment that lends itself to lights-out automation.

A standardized transport protocol is essential for full automation of backend burn-in and test. A tray format for burn-in and test of arrays of devices allows automated transport throughout the processes including probe, burn-in, test, trim, reflow, mark, sort and tape.

With standard interfaces, the tools and equipment can be rapidly adapted and reconfigured. Fixtures and change-over times are minimized. Process flow of bar coded trays can be handled automatically with minimal intervention.

Obviously, socket or probe downtime is a real impediment to full lights-out automation. Low or zero maintenance sockets, fixtures, and contactors are required. Self-cleaning and self-aligning contactors would ease the problem of eliminating manual intervention for maintenance.

Continuing increases in ball/pad density place further demands for reliable operation on contactor technologies of the future.

Looking to the future, flip-chip-, wafer-level packaging and stacked chips will place additional demands on contactor technology capable of supporting the higher contact density and automatic handling.

Improvements in technology for contactors, sockets, handlers and probes are needed to enable full automation of semiconductor backend production.

Some level of cooperation and agreements on standards and protocols in necessary. The technical community has seen the need and is beginning to respond. SEMI has organized CAST aimed at standards and improvements in the wafer test cell.

MicroConnections has initiated a Test-in-Tray User Group to explore standards and protocols in burn-in and test. More coordinated activity in this area is vital to our industry

1Excerpted from a VLSI Research interview with Tom Franz, July 25, 2007. 2T. Di Stefano in MicroConnections, Vol. 2, Nr. 4.

Could you have known your product had a fatal flaw?

Previously Published in August 2009

Our lives in a complex world are increasingly dependent upon ubiquitous electronic devices, many of which are prone to unpredictable failure, leading in some cases to catastrophic losses. A cell phone that dies when inadvertently dropped may be an inconvenience, but a defibrillator failure is a vastly greater concern.

The relevant question is could the failure have been predicted and possibly averted? Difficult, you say, but not impossible. Specifically, can latent defects be found and eliminated before failure?

A compelling case can be put forth that every effort should be made to detect latent defects, particularly for life-critical applications in medical, automotive and aerospace, where one bad connection may cost lives and spawn alarming headline articles in the popular press.

COMMON DEFECTS, MUNDANE CAUSES Although electronic systems are becoming unthinkably complex, commonly occurring latent defects often have rather mundane causes, such as a loose connector, a cracked circuit board, or electroplating along a trail of contamination.

Those who remember the PDP-8 lab computer would understand. When the computer failed, the first thing to try was unplug and plug-in circuit boards in an effort to jar the connectors back to life.

ROLM, a wildly successful company, was founded on the simple premise of offering a Data General Nova computer reworked with mil-spec connectors for added reliability.

Although technology has come a long way, latent defects remain a recurring problem. Moore’s Law has worked its wonders, but the basics of connectors and interconnect technology are littlechanged. Latent defects continue to plague interconnect in all its various forms.

Two heavyweights of interconnect technology, IBM and AMP (now Tyco), wrestled these issues to the ground years ago.1, 2

Test techniques were developed to detect certain classes of latent defects, primarily electrical opens that could lead to field failures in missioncritical systems.

ROOTING OUT POTENTIAL OPENS IBM, for example, has used measurement of non-linearity to detect and root out potential opens defects with outstanding success. Fieldfailure rates for circuit boards and interconnects in mainframe systems have been reduced to insignificance for decades.

Perhaps we can learn something from IBM and AMP about latent defect detection in other applications where assured functionality is becoming more important.

Interconnect failures are predominantly due to opens, which is simple enough to understand, but the specific mechanism of failure may be quite complex.

Candidate causes include stress corrosion, contact fritting, fatigue cracking, thermal expansion mismatch, electromigration and Kirkendall voiding.

At its root, most mechanisms are accelerated by current crowding, caused perhaps by a delaminating via, a poorly mated conductor, a cracked circuit trace and the like. It is this current crowding that can be detected by sophisticated means.

Electrical test currents passed through a constriction produce characteristic signals that may be detected and used to flag the presence of the defect causing the constriction.2

High levels of current crowding cause material in the constriction to heat and to increase in resistance, for example, by 0.39% per °C in copper.

The periodic resistance rise caused by the passage of a signal through a constriction is easily detectable by sensing the resulting intermodulation distortion.


In the simplest case, latent defects are detected by measuring the harmonic generation caused by a pure ac signal passing through a current constriction associated with the defect.

Essentials of the effect are illustrated in the figure at left, which shows local heating due to a sinusoidal current passing through a notch, a model representation of a constriction.

A sine wave superposed on a dc current generates a second harmonic signal when passed through such a constriction. Harmonic detection equipment is used to find latent defects so they may be eliminated as a cause of failure in high end systems.

INDUSTRY PARTICIPATION It is appropriate and timely that the electronics industry, specifically the medical and aerospace segments, take a more active role in detecting and eliminating defects. The techniques and understanding to do so are at hand.

REFERENCES 1. J.H. Whitley, “Method and Means for Measuring Constriction Resistance Based on Nonlinearity,” U.S. Patent 3,500,188. 2. A. Halperin, T. Di Stefano and S. Chiang, “Latent Defect Detection Using

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We’ve Moved!

Centipede has a new facility in the heart of Silicon Valley:

41 Daggett Dr.
San Jose, CA 95134

Test-in-Tray User Group


A first Test-in-Tray User Group was held in Los Gatos on October 20 to highlight emerging test-in-tray solutions for back-end burn-in and test.

A Keynote by Dr. W. R. Bottoms outlined challenges of ever increasing density and performance needed for future computing systems. Invited talks explored parallel test methods using a tray format that allows full automation of the back end operations.

Participants included 50 leaders from memory, logic, MEMS, EMS and ATE.